library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity logicaselec is
Port ( --clk : in STD_LOGIC;
cc : out std_logic;
vf : in std_LOGIC;
qx : in std_LOGIC;
upas : in std_logic_vector (2 downto 0);
bus7 : in std_logic;
bus15 : in std_logic;
int : in std_logic; 
banderas : in std_logic_vector (7 downto 0);
prueba : in std_logic_vector (1 downto 0));

end logicaselec;
architecture Behavioral of logicaselec is

constant s0 : std_logic_vector(3 downto 0) := B"0000";
begin
process (prueba,vf,qx)
begin
--if prueba then
--			cc='0'
end process;
end Behavioral;